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Features
General
* * * * * * * High-performance, Low-power secureAVR TM Enhanced RISC Architecture
- 135 Powerful Instructions (Most Executed in a Single Clock Cycle) Low Power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to 4000V Operating Ranges: 1.62 to 5.50V Compliant with GSM, 3GPP and EMV 2000 Specifications, PC Industry Compatible Available in Wafers, Modules, and Industry-standard Packages
Memory
* 288K Bytes of ROM Program Memory * 144K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Bytes
- 1 to 128-byte Program / Erase - 1ms Program / 1ms Erase - Typically 500,000 Write/Erase Cycles at a Temperature of 25 oC - 10 Years Data Retention * 6K bytes RAM Memory
Secure Microcontroller for Smart Cards AT90SC288144RU Summary
Peripherals
* One I/O Port * One ISO 7816 Controller * * * * * * *
- Up to 625 Kbps at 5 MHz - Compliant with T=0 and T=1 Protocols Programmable Internal Oscillator (Up to 30 MHz for internal CPU Clock) Two 16-bit Timers Random Number Generator (RNG) 2-level Interrupt Controller Hardware DES and Triple DES DPA Resistant Checksum Accelerator CRC16 & 32 Engine (Compliant with ISO/IEC 3309)
Security
* * * * * *
Dedicated Hardware for Protection Against SPA/DPA/SEMA/DEMA Attacks Advanced Protection Against Physical Attack, Including Active Shield, Environmental Protection Systems Voltage Monitor Frequency Monitor Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
* Voyager Emulation Platform (ATV4) to Support Software Development * IAR Embedded Workbench(R) V4.20 Debugger or Atmel's AVR Studio(R) Version 4.07 or
Above
* Software Libraries and Application Notes
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Note: This is a summary document. A complete document will be available under NDA. For more information, please contact your local Atmel sales office.
Description
The AT90SC288144RU is a low-power, high-performance, 8/16-bit microcontroller with ROM program memory, EEPROM memory, based on the secureAVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90SC288144RU achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 general-purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The AT90SC288144RU uses the secureAVR architecture that allows the linear addressing of up to 8M bytes of code and up to 16M bytes of data as well as a number of new functional and security features. The AT90SC288144RU features 144K bytes of high-performance EEPROM (fast erase/write time, high endurance). The ability to map the EEPROM in the code space allows parts of the program memory to be reprogrammed in-system. Additional security features include logical scrambling on program data and addresses, power analysis countermeasures, and memory accesses controlled by a supervisor mode. Figure 1 shows a block diagram of the AT90SC288144RU
Figure 1. AT90SC288144RU secureAVR Enhanced RISC Architecture
Data Bus 8-bit OTP EEPROM User Memory Program Memory 16 Instruction Register 16 ALU Instruction Decoder 16 Control Lines Status Register DPA Counter measures CRC and Checksum Accelerator 8 8 General Purpose Registers X
Y Z CLK
Access Control
RNG
Secure Control
GND
VCC
RAM Data Memory Interrupt Unit Access Control ISO 7816 Controller ISO 7816 I/O Port 0 Timer 0 Timer 1 Reset Circuit RST
IN/OUT0
PC
8
2
AT90SC288144RU
6543AS-SPIC-080107
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6543AS-SPIC-080107

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